As semiconductor devices have become more highly integrated, structures including transistors multi-stacked within a limited area of a semiconductor substrate have been developed. A static random access memory (SRAM) device, for example, may use a stacked structure of transistors.
FIG. 1 is an equivalent circuit diagram of a conventional inverter. Referring to FIG. 1, a gate electrode of a first transistor TR1, (e.g., an n-channel metal oxide semiconductor (NMOS) transistor) and a gate electrode of a second transistor TR2, (e.g., a p-channel MOS (PMOS) transistor) are commonly connected to an input signal Vin line. A source of the second transistor TR2 is connected to a power voltage VDD line, and drains C of the second transistor TR2 and the first transistor TR1 are connected to an output line Vout. A source of the first transistor TR1 is connected to a ground voltage VSS line. The device having the above circuit structure may operate as an inverter.
The inverter of FIG. 1 may be formed by arranging the first and second transistors TR1 and TR2 (of different conductivity types) on the same plane. To provide a more highly integrated device, the inverter may be configured in a stacked structure with the second transistor TR2 stacked on the first transistor TR1.
FIG. 2 is an equivalent circuit diagram of a conventional full CMOS SRAM device. Referring to FIG. 2, the conventional full CMOS SRAM device includes two inverters and two transfer transistors TR3 and TR6. The inverters are configured with driving transistors TR1 and TR4, (e.g., NMOS transistors) and load transistors TR2 and TR5, (e.g., PMOS transistors) with the two inverters being cross-coupled to each other. A source of each load transistor TR2 and TR5 is connected to a power voltage VDD line, and a source of each driving transistor TR1 and TR4 is connected to a ground voltage VSS line. Gate electrodes of the transfer transistors TR3 and TR6 are connected to a word line, and one source/drain of each of the transfer transistors is connected to a bit line BL or BL. The other one of the source/drain of each transfer transistor TR3 and TR6, a drain of each driving transistor TR1 and TR4, and a drain of each load transistor TR2 and TR5 are connected to respective common terminals/contacts C1 and C2. In addition, the common terminal C1 is connected to the gate electrode of the driving transistor TR4 and the gate electrode of the load transistor TR5. Likewise, the common terminal C2 is connected to the gate electrodes of the driving transistor TR1 and the gate electrode of the load transistor TR2.
Although the SRAM device may be formed by arranging the six transistors TR1 to TR6 on the same plane, the SRAM device may be formed by arranging the driving transistors TR1 and TR4 at a lower layer, the load transistors TR2 and TR5 on the driving transistors TR1 and TR4 on a middle layer, and the transfer transistors TR3 and TR6 on the load transistors TR2 and TR5 on an upper layer. Accordingly it may be possible to enhance an integration density of the device employing this stacked structure.
A conventional method of forming the semiconductor device having the stacked transistors will be discussed below with reference to FIGS. 3 to 5. Referring to FIG. 3, a first transistor provided with a first gate pattern 202 and source/drain regions 204 is formed on a semiconductor substrate 200, and an etch stop layer 206 is conformally formed on the resulting structure. A first insulating layer 208 is stacked on the etch stop layer 206. The first interlayer insulating layer 208 and the etch stop layer 206 are patterned in sequence to form a contact hole 210 exposing the semiconductor substrate 200. An epitaxial contact plug 212 is formed to fill the contact hole 210 through a selective epitaxial growth (SEG) process. A semiconductor single crystalline layer 214 is formed on the entire surface of the semiconductor substrate 200. A second transistor configured with a second gate pattern 216 and source/drain regions 218 may be formed on the semiconductor single crystalline layer 214. A second interlayer insulating layer 220 is formed to cover the resulting structure. While not shown in the drawings, a plurality of transistors may be formed on an additional semiconductor layer(s) by repeating the above processes including the SEG process.
Thereafter, referring to FIGS. 4 and 5, the second interlayer insulating layer 220, the semiconductor single crystalline layer 214 and the epitaxial contact plug 212 are etched to form a common contact hole 222 for a common contact plug (not shown) to commonly connect the transistors on respective layers to each other. In general, the common contact plug may be formed at the location of the epitaxial contact plug 212 for the sake of expediency of the manufacturing process. Since the common contact hole 222 is formed by etching a few layers in sequence, it may have a high aspect ratio. In addition, when forming the common contact hole 222, the epitaxial contact plug 212 formed of single crystal silicon is etched to expose the semiconductor substrate 200 (which is also formed of single crystal silicon) so that there may not be an etch selectivity between the epitaxial contact plug 212 and the semiconductor substrate 200. Therefore, the etching process may not be stopped using an end-point detection technique but should be stopped using a time-etch technique.
Because the etch stop point may not be accurately controlled during the etching process, there may remain a portion of the epitaxial contact plug 212 so that the semiconductor substrate 200 is not exposed, as illustrated in FIG. 4. On the contrary, if the etching process is excessively performed, the semiconductor substrate 200 may be excessively etched, as illustrated in FIG. 5. If a portion of the epitaxial contact plug 212 remains so that the semiconductor substrate 200 is not exposed as shown in FIG. 4, a resistance of the common contact may be undesirably high because the epitaxial contact plug 212 may be formed of undoped single crystal silicon having a high resistance. Meanwhile, if the semiconductor substrate 200 is over-etched, a leakage current may increase due to an etch loss.
Therefore, accurate control of the etching process may be desired so that the etch can be stopped when the semiconductor substrate is exposed. To this end, an etch stop layer may be used. However, because the epitaxial contact plug 212 is formed to penetrate through the etch stop layer 206 and because the common contact hole 222 is formed to penetrate through the epitaxial contact plug 212, the etch stop layer 206 may not be present at the location where the common contact hole 222 will be formed, when forming the common contact hole 222. Accordingly, accurate formation of the common contact hole 222 may be difficult using the etch stop layer according to conventional methods of forming semiconductor devices having stacked transistors.